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INTEGRATED CIRCUITS
DATA SHEET
UDA1324TS Ultra low-voltage stereo filter DAC
Preliminary specification Supersedes data of 1999 Oct 12 File under Integrated Circuits, IC01 2000 Jan 20
Philips Semiconductors
Preliminary specification
Ultra low-voltage stereo filter DAC
FEATURES General * Low power consumption * Ultra low power supply voltage from 1.9 to 2.7 V * Selectable control via L3 microcontroller interface or via static pin control * System clock frequencies of 256fs, 384fs and 512fs selectable via L3 interface or 256fs and 384fs via static pin control * Supports sampling frequencies (fs) from 16 to 48 kHz * Integrated digital filter plus non inverting Digital-to-Analog Converter (DAC) * No analog post filtering required for DAC * Slave mode only applications * Easy application * Small package size (SSOP16). Multiple format input interface * L3 mode: I2S-bus, MSB-justified or LSB-justified 16, 18 and 20 bits format compatible * Static pin mode: I2S-bus or LSB-justified 16, 18 and 20 bits format compatible * 1fs input format data rate. DAC digital sound processing * Digital logarithmic volume control in L3 mode * Digital de-emphasis selection for 32, 44.1 and 48 kHz sampling frequencies in L3 mode or 44.1 kHz sampling frequency in static pin mode * Soft mute control in static pin mode or in L3 mode. Advanced audio configuration * Stereo line output (volume control in L3 mode) * High linearity, wide dynamic range and low distortion. ORDERING INFORMATION TYPE NUMBER UDA1324TS PACKAGE NAME SSOP16 DESCRIPTION
UDA1324TS
APPLICATIONS * Portable digital audio equipment. GENERAL DESCRIPTION The UDA1324TS is a single-chip stereo DAC employing bitstream conversion techniques. The ultra low-voltage requirements make the device eminently suitable for use in portable digital audio equipment which incorporates playback functions. The UDA1324TS supports the I2S-bus data format with word lengths of up to 20 bits, the MSB-justified data format with word lengths of up to 20 bits and the LSB-justified serial data format with word lengths of 16, 18 and 20 bits. The UDA1324TS can be used in two modes: L3 mode or static pin mode. In the L3 mode, all digital sound processing features must be controlled via the L3 interface, including the selection of the system clock setting. In the two static modes, the UDA1324TS can be operated in the 256fs and 384fs system clock mode. Muting, de-emphasis for 44.1 kHz and four digital input formats (I2S-bus or LSB-justified 16, 18 and 20 bits) can be selected via static pins. The L3 interface cannot be used in this application mode, so volume control is not available in this mode.
VERSION SOT369-1
plastic shrink small outline package; 16 leads; body width 4.4 mm
2000 Jan 20
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Philips Semiconductors
Preliminary specification
Ultra low-voltage stereo filter DAC
QUICK REFERENCE DATA SYMBOL Supplies VDDA VDDD IDDA IDDD DAC; note 1 Vo(rms) (THD + N)/S S/N cs Tamb Notes 1. The analog performance figures are measured at 2.0 V supply voltage. 2. The DAC output voltage scales linearly with the power supply voltage. BLOCK DIAGRAM output voltage (RMS value) note 2 - - - - - -40 analog supply voltage digital supply voltage analog supply current digital supply current VDDA = 2.0 V VDDD = 2.0 V 1.9 1.9 - - PARAMETER CONDITIONS MIN.
UDA1324TS
TYP.
MAX.
UNIT
2.0 2.0 3.0 1.5
2.7 2.7 - - - -78 - - - +70
V V mA mA
500 -83 -36 97 100 -
mV dB dB dB dB
C
total harmonic distortion-plus-noise to at 0 dB signal ratio at -60 dB; A-weighted signal-to-noise ratio channel separation ambient temperature code = 0; A-weighted
handbook, full pagewidth
VDDD 4 1 2 3
VSSD 5 7 11 DIGITAL INTERFACE CONTROL INTERFACE 10 9 8 APPSEL APPL0 APPL1 APPL2 APPL3
BCK WS DATAI
UDA1324TS
6
VOLUME/MUTE/DE-EMPHASIS
SYSCLK
INTERPOLATION FILTER
NOISE SHAPER
VOUTL
14
DAC
DAC
16
VOUTR
13 VDDA
15 VSSA
12 Vref(DAC)
MBK770
Fig.1 Block diagram.
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Philips Semiconductors
Preliminary specification
Ultra low-voltage stereo filter DAC
PINNING SYMBOL BCK WS DATAI VDDD VSSD SYSCLK APPSEL APPL3 APPL2 APPL1 APPL0 Vref(DAC) VDDA VOUTL VSSA VOUTR PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DESCRIPTION bit clock input word select input data input digital supply voltage digital ground system clock input: 256fs, 384fs and 512fs application mode select input application input pin 3 application input pin 2 application input pin 1 application input pin 0 DAC reference voltage analog supply voltage for DAC left channel output analog ground for DAC right channel output Table 1 FUNCTIONAL DESCRIPTION System clock
UDA1324TS
The UDA1324TS operates in the slave mode only. Therefore, in all applications the system devices must provide the system clock. The system frequency (fsys) is selectable and depends on the application mode. The options are: 256fs, 384fs and 512fs for the L3 mode and 256fs or 384fs for the static pin mode. The system clock must be locked in frequency to the digital interface input signals. The UDA1324TS supports sampling frequencies (fs) from 16 to 48 kHz. Application modes The application mode can be set with the three-level pin APPSEL (see Table 1): * L3 mode * Static pin mode with fsys = 384fs * Static pin mode with fsys = 256fs. Selecting application mode and system clock frequency via pin APPSEL MODE L3 mode static pin mode fsys 256fs, 384fs or 512fs 384fs 256fs
VOLTAGE ON PIN APPSEL VSSD 0.5VDDD
handbook, halfpage
VDDD
BCK 1 WS 2 DATAI 3 VDDD 4 VSSD 5 16 VOUTR 15 VSSA 14 VOUTL 13 VDDA 12 Vref(DAC) 11 APPL0 10 APPL1 9
MBK769
The function of an application input pin (active HIGH) depends on the application mode (see Table 2). Table 2 Functions of application input pins FUNCTION PIN L3 MODE STATIC PIN MODE MUTE DEEM SF0 SF1 APPL0 APPL1 APPL2 APPL3 TEST L3CLOCK L3MODE L3DATA
UDA1324TS
SYSCLK 6 APPSEL 7 APPL3 8
APPL2
Fig.2 Pin configuration.
For example, in the static pin mode the output signal can be soft muted by setting pin APPL0 to HIGH. De-emphasis can be switched on for 44.1 kHz by setting pin APPL1 to HIGH; setting pin APPL1 to LOW will disable de-emphasis.
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Philips Semiconductors
Preliminary specification
Ultra low-voltage stereo filter DAC
In the L3 mode, pin APPL0 must be set to LOW. It should be noted that when the L3 mode is used, an initialization must be performed when the IC is powered-up. Digital interface DATA FORMATS The digital interface of the UDA1324TS supports multiple format inputs (see Fig.3). Left and right data-channel words are time multiplexed. The WS signal must have a 50% duty factor for all LSB-justified formats. The BCK clock can be up to 64fs, or in other words the BCK frequency is 64 times the Word Select (WS) frequency or less: fBCK 64 x fWS. Important: the WS edge MUST fall on the negative edge of the BCK at all times for proper operation of the digital interface. The UDA1324TS also accepts double speed data for double speed data monitoring purposes. L3 MODE * I2S-bus format with data word length of up to 20 bits * MSB-justified format with data word length up to 20 bits * LSB-justified format with data word length of 16, 18 or 20 bits. STATIC PIN MODE * I2S-bus format with data word length of up to 20 bits * LSB-justified format with data word length of 16, 18 or 20 bits. These four formats are selectable via the static pin codes SF0 and SF1 (see Table 3). Table 3 Input format selection using SF0 and SF1 FORMAT I2S-bus LSB-justified 16 bits LSB-justified 18 bits LSB-justified 20 bits SF0 0 0 1 1 SF1 0 1 0 1 Interpolation filter
UDA1324TS
The digital filter interpolates from 1fs to 128fs by cascading a recursive filter and a FIR filter (see Table 4). Table 4 Interpolation filter characteristics CONDITION 0 to 0.45fs >0.55fs 0 to 0.45fs VALUE (dB) 0.1 -50 108
ITEM Pass-band ripple Stop band Dynamic range Noise shaper
The 3rd-order noise shaper operates at 128fs. It shifts in-band quantization noise to frequencies well above the audio band. This noise shaping technique enables high signal-to-noise ratios to be achieved. The noise shaper output is converted into an analog signal using a Filter Stream Digital-to-Analog Converter (FSDAC). Filter stream DAC The FSDAC is a semi-digital reconstruction filter that converts the 1-bit data stream of the noise shaper to an analog output voltage. The filter coefficients are implemented as current sources and are summed at virtual ground of the output operational amplifier. In this way very high signal-to-noise performance and low clock jitter sensitivity is achieved. A post filter is not needed due to the inherent filter function of the DAC. On-board amplifiers convert the FSDAC output current to an output voltage capable of driving a line output. The output voltage of the FSDAC scales linearly with the power supply voltage.
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ndbook, full pagewidth
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Philips Semiconductors
Ultra low-voltage stereo filter DAC
WS 1 BCK 2 3
LEFT >=8 1 2 3
RIGHT >=8
DATA
MSB
B2
MSB
B2
MSB
I2S-BUS FORMAT WS 1 BCK 2 LEFT 3 >=8 1 2
RIGHT 3 >=8
DATA
MSB
B2
LSB
MSB
B2
LSB
MSB
B2
MSB-JUSTIFIED FORMAT WS LEFT 16 BCK 15 2 1
RIGHT 16 15 2 1
DATA
MSB
B2
B15 LSB LSB-JUSTIFIED FORMAT 16 BITS
MSB
B2
B15 LSB
WS
LEFT 18 17 16 15 2 1
RIGHT 18 17 16 15 2 1
BCK
DATA
MSB
B2
B3
B4
B17 LSB LSB-JUSTIFIED FORMAT 18 BITS
MSB
B2
B3
B4
B17 LSB
WS
LEFT 20 19 18 17 16 15 2 1
RIGHT 20 19 18 17 16 15 2 1
BCK
DATA
MSB
B2
B3
B4
B5
B6
B19 LSB LSB-JUSTIFIED FORMAT 20 BITS
MSB
B2
B3
B4
B5
B6
B19 LSB
Preliminary specification
WS 24 BCK 23 22 21
LEFT 20 19 18 17 16 15 2 1 24 23 22 21
RIGHT 20 19 18 17 16 15 2 1
UDA1324TS
DATA
MSB
B2
B3
B4
B5
B6
B7
B8
B9
B10
B23 LSB LSB-JUSTIFIED FORMAT 24 BITS
MSB
B2
B3
B4
B5
B6
B7
B8
B9
B10
B23 LSB
MBL121
Fig.3 Digital interface input data formats.
Philips Semiconductors
Preliminary specification
Ultra low-voltage stereo filter DAC
L3 INTERFACE The following system and digital sound processing features can be controlled in the L3 mode of the UDA1324TS: * System clock frequency * Data input format * De-emphasis for 32, 44.1 and 48 kHz * Volume * Soft mute. The exchange of data and control information between the microcontroller and the UDA1324TS is accomplished through a serial interface comprising the following signals: * L3DATA * L3MODE * L3CLOCK. Information transfer through the microcontroller bus is organized in accordance with the L3 interface format, in which two different modes of operation can be distinguished: address mode and data transfer mode. Address mode The address mode (see Fig.4) is required to select a device communicating via the L3 interface and to define the destination registers for the data transfer mode. Data bits 7 to 2 represent a 6-bit device address where bit 7 is the MSB. The address of the UDA1324TS is 000101 (bit 7 to bit 2). If the UDA1324TS receives a different address, it will deselect its microcontroller interface logic. Data transfer mode The selected address remains active during subsequent data transfers until the UDA1324TS receives a new address command. Registers
UDA1324TS
The fundamental timing of data transfers (see Fig.5) is essentially the same as the address mode. The maximum input clock frequency and data rate is 64fs. Data transfer can only be in one direction, consisting of input to the UDA1324TS to program sound processing and other functional features. All data transfers are by 8-bit bytes. Data will be stored in the UDA1324TS after reception of a complete byte. A multi-byte transfer is illustrated in Fig.6.
The sound processing and other feature values are stored in independent registers. The first selection of the registers is achieved by the choice of data type that is transferred. This is performed in the address mode using bit 1 and bit 0 (see Table 5). Table 5 BIT 1 0 0 1 1 Selection of data transfer BIT 0 0 1 0 1 not used status (system clock frequency, data input format) not used TRANSFER data (volume, de-emphasis, mute)
The second selection is performed by the 2 MSBs of the data byte (bit 7 and bit 6). The other bits in the data byte (bit 5 to bit 0) represent the value that is placed in the selected registers. The `status' settings are given in Table 6 and the `data' settings are given in Table 7.
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Philips Semiconductors
Preliminary specification
Ultra low-voltage stereo filter DAC
UDA1324TS
handbook, full pagewidth
L3MODE th(L3)A tCLK(L3)L tsu(L3)A L3CLOCK tCLK(L3)H th(L3)A tsu(L3)A
Tcy(CLK)(L3) tsu(L3)DA th(L3)DA
L3DATA
BIT 0
BIT 7
MGL723
Fig.4 Timing address mode.
handbook, full pagewidth
tstp(L3)
tstp(L3)
L3MODE tCLK(L3)L tsu(L3)D tCLK(L3)H Tcy(CLK)L3 th(L3)D
L3CLOCK
tsu(L3)DA
th(L3)DA
L3DATA WRITE
BIT 0
BIT 7
MGL882
Fig.5 Timing data transfer mode.
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Philips Semiconductors
Preliminary specification
Ultra low-voltage stereo filter DAC
UDA1324TS
handbook, full pagewidth
tstp(L3)
L3MODE
L3CLOCK
L3DATA
address
data byte #1
data byte #2
address
MGL725
Fig.6 Multibyte data transfer.
Programming the features When the data transfer of type `status' is selected, the features for the system clock frequency and the data input format can be controlled. Table 6 BIT 7 0 1 Data transfer of type `status' BIT 6 0 0 BIT 5 SC1 0 BIT 4 SC0 0 BIT 3 IF2 0 BIT 2 IF1 0 BIT 1 IF0 0 BIT 0 0 0 REGISTER SELECTED SC = system clock frequency (2 bits); see Table 8 IF = data input format (3 bits); see Table 9 not used
When the data transfer of type `data' is selected, the features for volume, de-emphasis and mute can be controlled. Table 7 BIT 7 0 0 1 1 Data transfer of type `data' BIT 6 0 1 0 1 BIT 5 VC5 0 0 0 BIT 4 VC4 0 DE1 0 BIT 3 VC3 0 DE0 0 BIT 2 VC2 0 MT 0 BIT 1 VC1 0 0 0 BIT 0 VC0 0 0 1 not used DE = de-emphasis (2 bits); see Table 10 MT = mute (1 bit); see Table 12 default setting REGISTER SELECTED VC = volume control (6 bits); see Table 11
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Philips Semiconductors
Preliminary specification
Ultra low-voltage stereo filter DAC
SYSTEM CLOCK FREQUENCY The system clock frequency is a 2-bit value to select the external clock frequency. Table 8 SC1 0 0 1 1 System clock settings SC0 0 1 0 1 512fs 384fs 256fs not used FUNCTION VOLUME CONTROL
UDA1324TS
The volume control is a 6-bit value to program the volume attenuation from 0 to -60 dB and - dB in steps of 1 dB. Table 11 Volume settings VC5 0 0 0 0 : 1 1 1 1 1 1 1 1 1 1 1 1 1 MUTE VC4 0 0 0 0 : 1 1 1 1 1 1 1 1 1 1 1 1 1 VC3 0 0 0 0 : 0 0 0 0 0 1 1 1 1 1 1 1 1 VC2 0 0 0 0 : 0 1 1 1 1 0 0 0 0 1 1 1 1 VC1 0 0 1 1 : 1 0 0 1 1 0 0 1 1 0 0 1 1 VC0 0 1 0 1 : 1 0 1 0 1 0 1 0 1 0 1 0 1 -60 - -57 VOLUME (dB) 0 0 -1 -2 : -51 -52 -54
DATA FORMAT The data format is a 3-bit value to select the used data format. Table 9 IF2 0 0 0 0 1 1 1 1 Data input format settings IF1 0 0 1 1 0 0 1 1 IF0 0 1 0 1 0 1 0 1 I2S-bus LSB-justified 16 bits LSB-justified 18 bits LSB-justified 20 bits MSB-justified not used not used not used FORMAT
DE-EMPHASIS De-emphasis is a 2-bit value to enable the digital de-emphasis filter. Table 10 De-emphasis settings DE1 0 0 1 1 DE0 0 1 0 1 FUNCTION no de-emphasis de-emphasis, 32 kHz de-emphasis, 44.1 kHz de-emphasis, 48 kHz
Mute is a 1-bit value to enable the digital mute. Table 12 Mute setting MT 0 1 no muting muting FUNCTION
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Philips Semiconductors
Preliminary specification
Ultra low-voltage stereo filter DAC
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL VDDD VDDA Txtal(max) Tstg Tamb Ves Isc(DAC) PARAMETER digital supply voltage analog supply voltage maximum crystal temperature storage temperature ambient temperature electrostatic handling voltage short-circuit current of DAC note 2 note 3 note 4 output short-circuited to VSSA(DAC) output short-circuited to VDDA(DAC) Notes 1. All supply connections must be made to the same power supply. - - note 1 note 1 CONDITIONS - - - -65 -40 -3000 -300 MIN.
UDA1324TS
MAX. 5.0 5.0 150 +125 +85 +3000 +300 450 300
UNIT V V C C C V V mA mA
2. Equivalent to discharging a 100 pF capacitor via a 1.5 k series resistor, except pin 14 which can withstand ESD pulses of -2500 to +2500 V. 3. Equivalent to discharging a 200 pF capacitor via a 2.5 H series inductor. 4. Short-circuit test at Tamb = 0 C and VDDA = 3 V. DAC operation after short-circuiting cannot be warranted. HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices. THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER thermal resistance from junction to ambient CONDITIONS in free air VALUE 190 UNIT K/W
QUALITY SPECIFICATION In accordance with "SNW-FQ-611-E". DC CHARACTERISTICS VDDD = VDDA = 2.0 V; Tamb = 25 C; RL = 5 k; all voltages referenced to ground (pins VSSA and VSSD); unless otherwise specified. SYMBOL Supplies VDDA VDDD IDDA IDDD analog supply voltage digital supply voltage analog supply current digital supply current note 1 note 1 operating operating 1.9 1.9 - - 2.0 2.0 3.0 1.5 2.7 2.7 - - V V mA mA PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
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Philips Semiconductors
Preliminary specification
Ultra low-voltage stereo filter DAC
UDA1324TS
SYMBOL
PARAMETER
CONDITIONS
MIN. - - - - - - -
TYP. -
MAX.
UNIT
Digital inputs: pins BCK, WS, DATAI, SYSCLK, APPL0, APPL1, APPL2 and APPL3 VIH VIL ILI CI VIH VIM VIL DAC Vref(DAC) Io(max) RO RL CL Notes 1. All supply connections must be made to the same external power supply unit. 2. When the DAC drives a capacitive load above 50 pF, a series resistance of 100 must be used to prevent oscillations in the output operational amplifier. AC CHARACTERISTICS VDDD = VDDA = 2.0 V; fi = 1 kHz; Tamb = 25 C; RL = 5 k; all voltages referenced to ground (pins VSSA and VSSD); unless otherwise specified. SYMBOL DAC Vo(rms) Vo (THD + N)/S output voltage (RMS value) unbalance voltage between channels total harmonic distortion-plus-noise to signal ratio signal-to-noise ratio channel separation power supply ripple rejection fripple = 1 kHz; ratio Vripple = 100 mV (p-p) at 0 dB at -60 dB; A-weighted code = 0; A-weighted - - - - - - - 500 0.1 -83 -36 97 100 50 - - -78 - - - - mV dB dB dB dB dB dB PARAMETER CONDITIONS MIN. TYP. MAX. UNIT reference voltage maximum output current output resistance load resistance load capacitance note 2 referenced to VSSA (THD + N)/S < 0.1%; RL = 5 k 0.45VDDA - - 3 - 0.5VDDA 0.16 0.15 - - 0.55VDDA - 2.0 - 50 V mA k pF HIGH-level input voltage LOW-level input voltage input leakage current input capacitance 0.8VDDD - - - 0.8VDDD 0.3VDDD -0.5 V V A pF 0.2VDDD 1 10
Three-level input: pin APPSEL HIGH-level input voltage MIDDLE-level input voltage LOW-level input voltage VDDD + 0.5 V 0.7VDDD 0.2VDDD V V
S/N cs PSRR
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Philips Semiconductors
Preliminary specification
Ultra low-voltage stereo filter DAC
UDA1324TS
TIMING VDDD = VDDA = 1.9 to 2.7 V; Tamb = -40 to +85 C; RL = 5 k; all voltages referenced to ground (pins VSSA and VSSD); unless otherwise specified. SYMBOL System clock (see Fig.7) Tsys system clock cycle time fsys = 256fs fsys = 384fs fsys = 512fs tCWL tCWH LOW-level system clock pulse width HIGH-level system clock pulse width fsys < 19.2 MHz fsys 19.2 MHz fsys < 19.2 MHz fsys 19.2 MHz Digital interface with I2S-bus (see Fig.8) Tcy(BCK) tBCKH tBCKL tr tf tsu(DATAI) th(DATAI) tsu(WS) th(WS) Tcy(CLK)L3 tCLK(L3)H tCLK(L3)L tsu(L3)A th(L3)A tsu(L3)D th(L3)D tsu(L3)DA th(L3)DA tstp(L3) bit clock cycle time bit clock HIGH time bit clock LOW time rise time fall time data input set-up time data input hold time word select set-up time word select hold time 300 100 100 - - 20 0 20 10 - - - - - - - - - - - - - - - - - - - - - - 20 20 - - - - - - - - - - - - - - ns ns ns ns ns ns ns ns ns 78 52 39 0.3Tsys 0.4Tsys 0.3Tsys 0.4Tsys 88 59 44 - - - - 244 162 122 0.7Tsys 0.6Tsys 0.7Tsys 0.6Tsys ns ns ns ns ns ns ns PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Control L3 interface (see Figs 4 and 5) L3CLOCK cycle time L3CLOCK HIGH time L3CLOCK LOW time L3MODE set-up time for address mode L3MODE hold time for address mode L3MODE set-up time for data transfer mode L3MODE hold time for data transfer mode L3DATA set-up time for data transfer and address mode L3DATA hold time for data transfer and address mode L3MODE stop time for data transfer mode 500 250 250 190 190 190 190 190 30 190 ns ns ns ns ns ns ns ns ns ns
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Philips Semiconductors
Preliminary specification
Ultra low-voltage stereo filter DAC
UDA1324TS
handbook, full pagewidth
t CWH
t CWL Tsys
MGR984
Fig.7 System clock timing.
handbook, full pagewidth
WS th(WS) tf tsu(WS)
tBCKH tr BCK tBCKL Tcy(BCK) DATAI
tsu(DATAI) th(DATAI)
MGL880
Fig.8 I2S-bus timing.
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Philips Semiconductors
Preliminary specification
Ultra low-voltage stereo filter DAC
APPLICATION INFORMATION
UDA1324TS
handbook, full pagewidth
analog supply voltage R2 1
digital supply voltage R3 1
C1 100 F (16 V) C5 100 nF (63 V) VSSA system clock R1 47 BCK WS DATAI APPSEL SYSCLK 15 6
C6 100 nF (63 V) VDDA 13 5 VSSD 4 VOUTL C2 47 F (16 V) R5 10 k R4 100 left output VDDD
14 1 2 3 7
UDA1324TS
APPL0 APPL1 APPL2 APPL3
16
VOUTR C3 47 F (16 V) R7 10 k
R6 100
right output
11 10 9 8 12 Vref(DAC) C7 100 nF (63 V) C4 47 F (16 V)
MBK771
Fig.9 Application diagram.
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Philips Semiconductors
Preliminary specification
Ultra low-voltage stereo filter DAC
PACKAGE OUTLINE SSOP16: plastic shrink small outline package; 16 leads; body width 4.4 mm
UDA1324TS
SOT369-1
D
E
A X
c y HE vM A
Z
16
9
Q A2 pin 1 index A1 (A 3) Lp L A
1
e bp
8
wM detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.5 A1 0.15 0.00 A2 1.4 1.2 A3 0.25 bp 0.32 0.20 c 0.25 0.13 D (1) 5.30 5.10 E (1) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1.0 Lp 0.75 0.45 Q 0.65 0.45 v 0.2 w 0.13 y 0.1 Z (1) 0.48 0.18 10 0o
o
Note 1. Plastic or metal protrusions of 0.20 mm maximum per side are not included. OUTLINE VERSION SOT369-1 REFERENCES IEC JEDEC MO-152 EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-02-04 99-12-27
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Philips Semiconductors
Preliminary specification
Ultra low-voltage stereo filter DAC
SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 230 C. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. Manual soldering
UDA1324TS
If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
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Philips Semiconductors
Preliminary specification
Ultra low-voltage stereo filter DAC
Suitability of surface mount IC packages for wave and reflow soldering methods
UDA1324TS
SOLDERING METHOD PACKAGE WAVE BGA, LFBGA, SQFP, TFBGA HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS PLCC(3), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications. not suitable not not not suitable(2) recommended(3)(4) recommended(5) suitable REFLOW(1) suitable suitable suitable suitable suitable
2000 Jan 20
18
Philips Semiconductors
Preliminary specification
Ultra low-voltage stereo filter DAC
NOTES
UDA1324TS
2000 Jan 20
19
Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 2000
Internet: http://www.semiconductors.philips.com
SCA 69
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
545002/25/03/pp20
Date of release: 2000
Jan 20
Document order number:
9397 750 06676

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